1. Field of the Invention
The present invention relates to static timing analysis, and in particular to partitioning of an integrated circuit design to ensure fast, parallel, and accurate analysis. Notably, this partitioning allows redundancy, i.e. the sharing of objects between partitions, thereby ensuring complete timing paths for objects of the design and improving subsequent analysis.
2. Related Art
Static timing analysis (STA) is a method of estimating the expected timing of a circuit without performing simulation (which tends to be slow and complex). In STA, timing analysis can be carried out in an input-independent manner (hence the term “static”) to determine the worst-case delay of the circuits in the design over all possible input combinations. To provide fast, reasonably accurate estimates of circuit timing, STA relies on simplified delay models and minimizes consideration of the effects of signal interactions.
Notably, the size, and functional and physical complexity of integrated circuit designs continue to grow rapidly due to advancements in system integration, design techniques, and manufacturing technologies. As a result, it takes ever longer runtime, and demands ever more powerful computing hardware with ever larger capacity to perform full chip STA. Therefore, STA tools can increasingly become a major bottleneck in integrated circuit design flow.
Therefore, a need arises for techniques to increase the speed and reduce the monolithic machine memory requirement of STA while still ensuring accurate timing estimations.